What is a Hardware description language (HDL)
A hardware description language is a high-level programming language which provides special constructs with which we can model microelectronic circuits it is mainly used for
- Simulation
- Synthesis
- Documentation
In the beginning, the design of electronic circuits involved only fewer gates so the verification of the circuits was easy but as the design became complex the verification wasn’t easy, so the designers used hardware description language by which the circuits can be verified
Why do we need HDL
- It can be used to describe the circuit at a various level such as the behavior of a circuit, function of a circuit, structure of a circuit
- It could describe the timing of a circuit
- Express the concurrency of circuit operation
- Design can be done at a high implementation-independent level
- Easily explore design alternatives
- Architectural problems can be solved before implementation
- Automate mapping of high-level description to a technology-specific implementation
- Earlier design components can be reused
- Design data can be easily managed
- Designer can make a decision about cost, performance, and power earlier in the design process
- It will help the designers to design tools which can manipulate the design for verification, synthesis, optimization…
Difference between HDL and software programming language
A software programming language is a language which can be translated into machine instructions and then executed on the computer but HDL is a language with syntactic and semantic support for modeling the temporal behavior and spatial structure of the hardware
Introduction to Verilog
Verilog is a hardware description language by which we can describe the digital electronic system at multiple levels of abstraction
- Behavioral
- Structural
- Functional
Design specification of the digital circuits can be done by this
Advantages of Verilog
- It is easy to learn and use because the syntax is similar to C language
- Different levels of abstraction can be mixed at the same level
- Verilog is supported by logic synthesis tools
- The user can write custom C code to interact with the internal data structure of Verilog by using programming language interface
- It can be used in high-level system simulation
- Compact description
- Easy to edit
- Highly portable
- Rapid prototyping of design
Verilog simulator
Verilog XL is a simulator for Verilog HDL, it complies or runs a system model either interactively or in batch mode. State display and special waveforms are available. If simulated system spans several files, Verilog files can assemble regardless of the order of the files are specified in, it complies the entire system on each invocation, and because of that there are no intermediate objects files nor is there an explicit link phase.
Supported levels of Abstraction by Verilog
Behavioral
It describes a system by the flow of data between its functional block and it defines signal values when it changes, the behavior level describes the behavior of a design without implying any specific internal architecture
Register transfer level (RTL) or functional
It describes a system by the flow of the data and control signals between and within its functional blocks and it defines signal values with respect to a clock, RTL level describes the design architecture in sufficient detail that a synthesis tool can construct the circuit
Structural
It describes the system by connecting predefined components, it uses specific technology, low-level components when mapping from an RTL description to a gate-level netlist during synthesis.