Ladder diagram logic is a rule-based language, where rule gets executed sequentially in a continuous loop. It is suited where binary variables are required and where interlocking and sequencing of a binary is the primary control problem.
NOT logic do a simple inverting function. The input function is just inverted at the output. The truth table for the NOT logic is given here.
Two logic switches connected in series is the AND gate.
In AND logic the output will be activated only if both switches are activated at simultaneously. All other logical combination cannot activate the output.
The output will be actuated either one of the two switches is activated.
Switch B is latched with the Switch A, so the output will be activated if any of the switches is energized. The truth table is shown below.
NAND gate is simply using the invert switch in the OR gate.
The truth table is just the inversion of the AND gate.
NOR gate is a function using invert switches in the AND gate function.
The truth table for NOR gate is the opposite of the OR gate.
The output will be true only if both inputs are false.
The XOR or Exclusive-OR gate is a special form of OR function. An exclusive-or function built from a combination of AND, OR, and inverter (NOT) gates.
There is no limit to how many contacts per switch can be represented in a ladder diagram, this is a combination of two switches relay.
The output will be true only if one of the input is true. Same input generates False output.
TIMER : ON Delay timer
TON timer or the ON delay timers allow us to set a time delay in the program before enabling the output. Even after the input is made True, the timer wait to enable the output till the timer running ends. The time delay can be fixed in the TON block.
When we give a start instruction which is a logical TRUE instruction to the device, the TON logic timer holds the instruction for a time period which can be set in the timer.
TIMER: OFF Delay timer
TOFF timer or OFF Delay timer allows us to set a time delay before switching OFF the output. The TOF provide a time delay before the output will stop function.
When we give a stop instruction which is a logical FALSE instruction to the device, the TOF logic timer holds the instruction for a time period which can be set in the timer.